A SRAM device may be a semiconductor memory device. Information stored on an SRAM device may be left intact while power is supplied. Hence, it may not be necessary to periodically refresh the SRAM device. An integrity of the SRAM device may be smaller than the integrity of a DRAM device. However, power consumption may be lower and processing speed may be higher in the SRAM device. An SRAM cell may be composed of six transistors. These may include two pull down transistors, two pull up transistors, and two access transistors.
FIG. 1 is an example illustration of a cell layout of a related art SRAM device and FIG. 2 is an example sectional view taken along the line A-A of FIG. 1.
Referring to FIGS. 1 and 2, to form pull-down NMOS transistor 10a and pull-up PMOS transistor 10b, N-well 11a and P-well 11b may be formed on the silicon substrate. Active region 13 may be defined by device isolation layer 12 formed on a silicon substrate and a gate may be formed on the silicon substrate to cross active region 13. Source/drain 15a/15b may be formed in active regions 13 on both sides of gate 14. Source/drain 15a/15b and the gate may be connected to metal interconnection 17 thereon through contacts 16a, 16b, and 16c and silicide layers 18 may be formed on source/drain 15a/15b and gate 14.
In the SRAM cell having such a structure, a region in which contact 16b of PMOS drain 15b may be formed and a region in which contact 16a of NMOS source 15a may be vulnerable regions that may cause leakage current in relation with any read/memory operation of the SRAM device. However, the related art SRAM device may not be able to avoid lack of process margin that may be caused by the layout.
That is, as illustrated in FIG. 1, since contact 16b may be positioned at both ends of active region 13 in the case of PMOS 10b and contact 16a may be positioned in a bent part of active region 13 in the case of NMOS 10a, the margin of processes related to the active regions and the contacts may be lacking. In particular, in the case of NMOS 10a where contact 16a may be positioned in the bent part of active region 13, even when the contacts are slightly misaligned or when the size of the contacts are large, a leakage current characteristic of the SRAM device may be degraded.
Also, when contact 16a may be positioned in the bent part of active region 13, active region 13 may become sharp to secure a contact space. However, in this shape, stress may be concentrated and may affect the dislocation of active region 13. Hence, a sequential heat treatment process may be required.
Furthermore, although contact 16b of PMOS drain 15b and contact 16a of NMOS source 15a may be bound together through the metal interconnection as illustrated in FIG. 2, contact 16b and contact 16a are separated from each other using wide device isolation layer 12 to reduce the margin of the metal interconnection process, which can degrade the leakage current characteristic due to the alignment and size of the contacts.